1. Field of the Invention
The present invention relates to a plastic packaged semiconductor device, and, more particularly, to a structure surrounding electrodes of a semiconductor chip packaged in an epoxy resin.
2. Description of the Related Art
FIG. 1 shows the vicinity of an electrode of a semiconductor chip in a conventional plastic packaged semiconductor device. The conventional plastic packaged semiconductor device includes a Si substrate 1 for a semiconductor chip, an insulating film 2 made of SiO.sub.2 which is disposed on the Si substrate 1, an Al electrode 3 disposed on a suitable portion of the insulating film 2, and a fine metallic wire 4 made of Au, which is bonded at one end to the upper surface of the Al electrode 3. The other each of the fine metallic wire 4 is connected to one of the inner leads of a leadframe (not shown) on which the semiconductor chip is mounted. A protective layer 5 in the form of glass coating or Si oxide film is formed on the portion of the insulating film 2 where no Al electrode 3 is formed, and a package body 6 made of epoxy resin is molded to the Si substrate 1, the insulating film 2, the Al electrode 3, the fine metallic wires 4 and the protective layer 5.
Such a plastic packaged semiconductor device is manufactured by the following procedure: after the insulating film 2 is formed on the Si substrate 1, the Al electrode 3 and the protective layer 5 are formed on the insulating film 2, as shown in FIG. 2. Next, the end of the fine metallic wire 4 is bonded to the upper surface of the Al electrode 3, as shown in FIG. 3, and these components are then packaged in the package body 6.
In the above-described plastic packaged semiconductor device, the Si substrate 1, which is a major component of the semiconductor chip, has a linear expansion coefficient of 3.times.10.sup.-6, and the package body 6 made of epoxy resin has a linear expansion coefficient about 10 times that of the Si substrate 1. This mismatch between the expansion coefficients of the Si substrate 1 and the package body 6 is directly responsible for stresses induced on the surface of the semiconductor chip, i.e., at the boundary of the protective layer 5 or the Al electrode 3 and the package body 6, and the stresses lead to generation of gaps therebetween. Stresses may be induced when the plastic packaged semiconductor device is subjected to thermal shock, e.g., during temperature cycling conducted in a reliability test or during soldering of external leads of the semiconductor device.
In the above-described plastic packaged semiconductor device which has gaps formed between the semiconductor chip and the package body 6 and, in particular, between the Al electrode 3 and the package body 6, water may enter the gaps as time elapses, thereby corroding the Al electrode 3 and reducing the reliability of the semiconductor device.